The invention relates to a process for producing structured layers. Such structured layers are used in the semiconductor technology, and are customarily produced with lithographic processes. Generally, a radiation-sensitive resist is structured first and the structure is subsequently transferred to underlying layers in an etching step. Specifically, the following steps are carried out for that purpose:
applying a radiation-sensitive resist on the layer to be structured,
irradiating the resist while using a mask for the desired structure,
developing the resist layer to produce a resist structure,
etching away the layer to be structured at the open regions which are not covered by the developed resist layer, and
removing the remaining resist layer.
However, not all layers are compatible with such processes for structuring. This is true, in particular, when material layers that are very difficult to etch are involved, for example noble metals such as Au, Pt or platinum metals such as Ir or Pd as well as various oxide materials such as IrO2 or magnetic materials. In these situations, it is hardly possible to structure the layers or, during the structuring process, only very shallow-sides of the structures or even incorrect structuring such as undesired build-ups are formed. In such a situation, indirect structuring processes such as the so-called xe2x80x9clift-offxe2x80x9d process are resorted to. This type of process generally includes the steps:
providing a first layer,
structuring the first layer,
applying at least one further layer,
removing the remaining parts of the first layer, the parts of the at least one further layer which is applied on the first layer being automatically removed as well at these places. This leaves a structured second layer. A problem with this process is, however, the very limited suitability of the process when producing small structures, especially in the sub-xcexcm range. Another problem is that this process is difficult to use in a manufacturing process. Also, the material of the further layer is undesirably redeposited in part when it is removed together with the first layer.
In the field of semiconductor technology, these processes are used to produce individual components such as transistors, capacitors, and so forth. In addition to the problems mentioned above, a further disadvantage of the aforementioned processes is, however, that an elaborate process of applying and removing or eroding of layers is required in each case. Stringent requirements on the selectivity of the layer erosion need to be met specifically in the erosion steps, in order to erode only the desired layer. Further, the lithographic process is of only limited use and fails with a number of materials. These disadvantages can therefore lead to high production costs in component fabrication.
Lastly, there is also the possibility of directly structuring a layer, that is incompatible with any lithographic process, by carrying out layer erosion through ion bombardment or plasma etching. In this case, however, the difficulties arise that the erosion process takes place only slowly, only side edges of low gradient or steepness can be formed, and incorrect structuring can take place through re-deposition of the eroded layer material.
For details of the structuring processes mentioned above, reference is made to the current standard literature on semiconductor technology, such as xe2x80x9cTechnologie hochintegrierter Schaltungenxe2x80x9d (technology for highly integrated circuits), 2nd edition, Springer Publishers, Berlin 1996, D. Widmann, H. Mader, H. Friedrich, pages 29, 101, 102, and 166-168.
It is accordingly an object of the invention to provide a process for producing structured layers which overcomes the above-mentioned disadvantages of the heretofore-known processes of this general type and which simplifies the process of producing structured layers.
With the foregoing and other objects in view there is provided, in accordance with the invention, a process for producing structured layers, which comprises the steps of providing a base body, in particular a semiconductor body; providing a first layer on the base body; structuring the first layer by an at least partial local layer erosion for forming raised and recessed layer regions with edges formed at transitions between the raised and the recessed layer regions, the first layer being provided as a permanently remaining layer after the structuring step; and applying a second layer on the first layer and separating given layer regions of the second layer from one another using a height difference at the edges of the raised and the recessed regions, the edges of the raised regions acting as partition edges for the second layer.
A particular advantage is that, the first layer remains permanently on the base body after it is structured, and no further erosion of this structured layer is therefore necessary. The actual substrate layer may be used as the first layer in this case. Ideally, a material which allows relatively easy structuring is chosen as the first layer. The structuring of the second or the at least one further layer in individual regions results automatically from the height differences of the surface configuration of the first layer. One only has to take into account that the layer thickness of the further layer must be less than the height difference at the edges which are formed by adjacent raised and recessed regions. Ideally, the height difference between the raised and recessed layer regions is at least twice the layer thickness of the second or further layer, preferably from 2 to 5 times the layer thickness. These edges then act as partition edges, which provide for the separation of the raised regions of the further layer from the recessed regions of this layer in the vicinity of the edges. A particular advantage of this method is that the production of small structures in the layer to be structured is easier than with processes which require local erosion of the layer, and therefore inevitably entail sizable inaccuracies in the structuring of the layer.
Preferably, the first further layer is deposited using an application or deposition process with directional deposition characteristics, for example a collimated sputtering process, on the surface of the first layer, that is to say using a deposition process which ideally deposits only perpendicular to the layer plane. This avoids coating or covering the sides of flanks of the raised and recessed parts of the surface to be coated, and a clear separation of individual regions of the layer is obtained.
A clear separation of the individual layer regions in the vicinity of the edges may, alternatively or additionally, be obtained if, after the deposition of the at least one further layer, suitable layer erosion of the at least one further layer for example an etching step is carried out in order to remove an edge coverage. However, the layer erosion can then be carried out with substantially less stringent requirements on selectivity, edge gradient, or erosion rate than would be the case, for example, with direct structuring of the further layers.
An auxiliary layer may also be provided on the raised parts, which is chemically modified before the deposition of the at least one further layer in such a way that a volume expansion of this auxiliary layer takes place. This auxiliary layer will therefore protrude over the edges of the raised parts of the first layer and thus shades or masks the side edges of the raised parts. This is advantageous, in particular, when it is not possible to achieve the optimum gradient for the side edges, and the side edges therefore cannot be structured ideally perpendicular to the layer surface. Examples of suitable chemical modifications of the auxiliary layer include oxidation and nitriding. Examples of chemically modified auxiliary layers that may be produced thus include SiO2, Si3N4, TiOx or TaOx.
In a preferred mode of the invention, the raised parts of the first layer define the functionally active regions of the at least one further layer. In this case, it may be expedient to cover the recessed regions of the at least one further layer in such a way that it is suitable for functionally neutralizing these regions. These regions of a layer that are not needed are therefore neutralized in a relatively uncomplicated way, and are even further isolated from the functionally active regions. Depending on the property of the subsequent layers, this covering may actually be carried out using these subsequent layers themselves. In this case it is preferable, after the erosion of the first further layer, to carry out a conformal deposition of at least one further layer, that is to say this further layer is applied with essentially constant layer thickness over the entire surface. It is, however, also possible to provide a directionally controlled deposition of the further layers.
The described process can be used for producing integrated circuits, for example memory configurations or storage configurations, with the components of the integrated circuit being produced by the structuring of the layers.
With the object of the invention in view there is further provided a process for producing a memory configuration, which comprises providing a semiconductor body; embedding selection transistors in the semiconductor body and in an insulation layer provided on the semiconductor body; and producing electrical components of a memory configuration on a support layer provided on the semiconductor body by depositing further layers on a surface of the support layer and structuring the further layers by structuring the surface of the support layer and forming raised and recessed regions therein, the raised and the recessed regions having edges formed at transitions with a height difference between the raised and the recessed regions, the edges of the raised regions acting as partition edges for at least one of the further layers.
The memory configurations are, in particular, configured such that selection transistors are embedded in a semiconductor body and in an insulation layer applied to the semiconductor body, and electrical components, in particular storage capacitors, are configured on a support layer by depositing further layers for producing the components on the surface of the support layer. In this case, the insulation layer in which the selection transistors are embedded may also be used as the support layer. Structuring of the layers, which make up the components, may then be carried out according to the process of the invention in a straightforward way by structuring the surface of the support layer in raised and recessed regions. In this case, for example, raised parts in the support layer may be structured already in such a way that they directly dictate the shape and position of a component, for example those of a storage capacitor. The component, in this case the storage capacitor, is then created automatically by the subsequent material deposits on the raised part of the support layer.
Thus, in order to produce storage capacitors, a first electrode layer for a first capacitor electrode of the storage capacitors is firstly deposited using an deposition process with directional deposition characteristics, for example by collimated deposition such as a sputtering process, on the surface of the support layer. The storage dielectric as well as a second electrode layer are deposited over this first electrode layer. The deposition of these two layers may be carried out by conformal deposition and by collimated application, with a combination of the two kinds of application being possible. Both dielectric, and ferroelectric substances are preferably provided as the material for the storage dielectric. The electrode material should be tailored to the desired function of the capacitor and the other process parameters for fabricating the memory configuration should also be taken into account when selecting the electrode material as well as the other layers that are used. For example, to produce DRAM OR FRAM memory configurations with a dielectric having a high dielectric constant or a ferroelectric dielectric as the storage dielectric, oxide dielectrics such as SBT SrBi2Ta2O9, SBTN SrBi2 (Ta1xe2x88x92x Nbx) 2O9, PZT PbxZr1xe2x88x92xTiO3 or BST BaxSr1xe2x88x92xTiO3 with xxe2x89xa7 are possible. Other perovskite-like paraelectric or ferroelectric layers are, however, also conceivable. Since, to produce such storage capacitors for DRAM or FRAM memory configurations, relatively high temperatures of up to 800xc2x0 C. are necessary, suitable electrode materials such as noble metals or their oxides, for example platinum or platinum metals such as Ru, Os, Rh, Ir or Pd, must correspondingly be used in order to satisfy the stringent requirements when producing the capacitors.
In accordance with another mode of the invention, the raised regions are structured by forming trenches therein, and one of the further layers is conformally deposited with a layer thickness of at least one half of a width of the trenches in a subsequent structuring step.
In accordance with a further mode of the invention, the support layer is electrically connected by structuring a given raised region, providing a conducting connection to the support layer in the given raised region, removing the storage dielectric and the second electrode layer in an area of the given raised region, and connecting the first electrode layer in the area of the given raised region.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a process for producing structured layers, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.